In industrial applications, a control device usually performs a variety of control tasks at the same time in parallel. Since usually more automation tasks have to be executed than CPUs are available, the simultaneous execution of the automation tasks on a single or multi-core CPU is solved by a real time system which decomposes the different automation tasks into small pieces of code which are executed sequentially. Real time behavior of parallel automation tasks is reached, for example, by a real time operating system, an interrupt system including an interrupt controller, and semaphore concepts or prioritization concepts.
Contemporary control systems additionally provide a graphical visualization of automation relevant information. This graphical visualization is used in order to display operator graphics and to provide a human machine interface. Modern graphic adapters provide a significant calculation power with dozens or hundreds of parallel calculation units. The overall calculation unit of a graphics adapter is called a graphics processing unit (GPU). However, the GPU is exclusively used for graphic applications.
Recently, much of the research and development in the graphics architecture field has been concerned ways to improve the performance of three-dimensional (3D) computer graphics rendering. Graphics architecture is driven by the same advances in semiconductor technology that have driven general-purpose computer architecture.
Many of the same acceleration techniques have been used in this field, including pipelining and parallelism. The graphics rendering application, however, imposes special demands and makes available new opportunities. For example, since image display generally involves a large number of repetitive calculations, it can more easily exploit massive parallelism than can general-purpose computations.
According to US 2008198167 A1, a computing system has been developed which is capable of parallelizing the operation of multiple GPUs supported on external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem.
The computing system of US 2008198167 A1 includes a CPU memory space for storing one or more graphics-based applications, one or more CPUs for executing the graphics-based applications, and a bridge circuit operably connecting one or more CPUs and the CPU memory space. The bridge circuit includes an integrated graphics device (IGD) having one or more GPUs.
Furthermore, the computing system of US 2008198167 A1 includes one or more graphics cards supporting multiple GPUs and being connected to the bridge circuit by way of a data communication interface, a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation, a plurality of graphic processing pipelines (GPPLs), implemented using the GPUs, and an automatic mode control module.
In an illustrative embodiment of US 2008198167 A1, the IGD has one internal GPU, and the external graphics card(s) supports multiple GPUs. During the run-time of the graphics-based application, the automatic mode control module automatically controls the mode of parallel operation of the multi-mode parallel graphics rendering subsystem so that the GPUs are driven in a parallelized manner.
In US 2008276262 A1, a method and an apparatus are disclosed that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or GPUs concurrently. One or more executables are compiled online from a source having an existing executable for a type of physical compute devices different from the one or more physical compute devices.
Dependency relations among elements corresponding to scheduled executables are determined to select an executable to be executed by a plurality of threads concurrently in more than one of the physical compute devices. A thread initialized for executing an executable in a GPU of the physical compute devices are initialized for execution in another CPU of the physical compute devices if the GPU is busy with graphics processing threads.
Sources and existing executables for an application processing interface (API) function are stored in an API library to execute a plurality of executables in a plurality of physical compute devices, including the existing executables and online compiled executables from the sources.
All these developments are directed to the original purpose of the graphics adapters i.e. the rendering of graphical content as images or movies stored in a computer whereat the speed of the rendering as well as the resolution have been improved tremendously. Publications in this field of technology concentrate on the improving the performance of graphic adapters in order to improve the quality and speed of the rendering.
In other words, the increase of computational capability of the electronic processing units most notably with regard to graphics adapters has not been expected, in particular not to that extent coincidentally by means of parallelization of the calculation processes. This is possible due to the fact that graphic processing units dispose of a plurality of graphic processing pipelines supporting multiple modes of parallel operation.
Recently, major vendors and/or manufacturers of graphic adapters provide programming interfaces to execute arbitrary code on the graphical unit which is not designated to graphic tasks. Complex algorithms for video transcoding, solution of differential equations or finite element analysis can already utilize the GPU power. A use in industrial applications and in particular in automation applications however is not available at present.